A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS

This brief presents an input-data-jitter-tolerant injection-type clock and data recovery (CDR) circuit with a super-harmonic injection-locked ring oscillator (SH-ILRO). Unlike prior injection-type CDRs that utilize a power-hungry CML-type data injection path or for which the data rate is limited to the process-defined CMOS logic bandwidth, the proposed injection-type CDR achieves energy-efficient data edge injection. The proposed wide-bandwidth source follower-based edge detector extracts the input data edge energy efficiently. The proposed SH-ILRO enables quarter-rate injection-locking without high-speed injection selection logic. Fabricated in 65-nm CMOS, the prototype injection-type CDR consumes 19.08 mW at 12 Gb/s with 87-MHz jitter transfer bandwidth and more than 1.0 UIpp jitter tolerance at 20 MHz.